1. Field of the Invention
The present invention relates to a method and an apparatus thereof for testing a memory, more particularly, relates to a method and an apparatus thereof for testing a static random access memory (SRAM) in a burn-in test mode.
2. Description of the Prior Art
To ensure that a normal life failure rate of a static random access memory product meets or exceeds a design goal, a burn-in test is processed after the product is manufactured. In general, the static random access memory product has a plurality of memory cells. The purpose of the burn-in test is to accelerate effects of various failure mechanisms of the memory cells. When the burn-in test is processed, the memory cells of the SRAM are selected by turns and an exterior voltage higher than the supply voltage is applied to each of the selected memory cells to drive the selected memory cells to perform write and read operations repeatedly, thereby checking whether the selected memory cells are in a good state or in a bad state.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of an apparatus 10 for testing a static random access memory 20 according to the prior art. The static random access memory 20 comprises a plurality of memory cells 22 for storing data, a plurality of word lines 24, a plurality of first bit lines 26, and a plurality of second bit lines 28. Each of the memory cells 22 is coupled to a corresponding word line 24, a corresponding first bit line 26, and a corresponding second bit line 28. The apparatus 10 comprises a control circuit 12 for controlling operations of the apparatus 10, a power supply 12 for providing each element of the apparatus 10 withelectric power, a column decoder 16, and a row decoder 18. Each of the memory cells 22 is coupled to the power supply 14. When the apparatus 10 tests the static random access memory 20, the control circuit 12 controls the column decoder 16 and the row decoder 18 to select an appropriate number of memory cells 22 so as to perform write and read operations sequentially, and the power supply 14 applies a working voltage Vcc of +5V to the selected memory cells 22 until the apparatus 10 accomplishes the test.
Please refer to FIG. 2. FIG. 2 is a schematic circuit diagram of the memory cell 22. The memory cell 22 comprises a storage circuit 32, a first switch circuit 34, and a second switch circuit 36. The storage circuit 32 is coupled to the power supply 14 and is capable of storing at least one binary bit of data. The first switch circuit 34 and the second switch circuit 36xe2x80x2 are both coupled to the corresponding word line 24. The first switch circuit 34 is coupled to the corresponding first bit line 26, and the second switch circuit 36 is coupled to the corresponding second bit line 28. The memory cell 22 is composed of six metal-oxide-semiconductor field-effect transistors (MOSFETs) T1, T2, T3, T4, T5, and T6. The four transistors T1, T2, T5, and T6 are NMOS transistors, and the two transistors T3, and T4 are PMOS transistors. The storage circuit 32 is a complementary metal oxide semiconductor (CMOS) circuit composed of the NMOS storage transistors T1 and T2, and the PMOS load transistors T3 and T4. The first switch circuit 34 is composed of the NMOS access transistor T5, and the second switch circuit 36 is composed of the NMOS access transistor T6.
As mentioned above, when the apparatus 10 tests the static random access memory 20, the power supply 14 applies the working voltage Vcc of +5V to the selected memory cells until the test is completed. In a write operation of logic xe2x80x9c1xe2x80x9d data, the control circuit 12 applies a voltage to the word line 24 via the row decoder 18, thus, the transistors T5, and T6 are rendered conductive. Later, the control circuit 12 applies another voltage to the first bit line 26 via the column decoder 16, thus, a voltage gap is formed between the first bit line 26 and the second bit line 28, and node A goes high, so that the transistor T2 becomes conductive but the transistor T4 becomes non-conductive. As a result, node B goes low. In response to the voltage level of node B, the transistor T3 becomes conductive but the transistor T1 becomes non-conductive. Thus, node A goes high. To the contrary, in the case of logic xe2x80x9c0xe2x80x9d data write operation, the control circuit 12 also applies a voltage to the word line 24 via the row decoder 18, so that the transistors T5, and T6 are rendered conductive. Later, the control circuit 12 applies another voltage to the second bit line 28 via the column decoder, thus, another voltage gap is formed between the second bit line 28 and the first bit line 26, and node B goes high, so that the transistor T1 becomes conductive, but the transistor T3 becomes non-conductive. As a result, node A goes low. In response to the voltage level of node A, the transistor T4 becomes conductive but the transistor T2 becomes non-conductive, so that node B goes high. Briefly, data is stored as voltage levels with the two sides of the storage circuit 32 in opposite voltage configurations, that is, the node A is high and the node B is low in one state, and the node A is low and the node B is high in the other state. The following method is used to perform this operation:
(a) selecting an appropriate number of memory cells 22 to test, and applying the working voltage Vcc of +5V until the test is accomplished;
(b) applying a voltage to the word lines 24 coupled to the selected memory cells 22;
(c) forming voltage gaps between the first lines 26 and the second bit lines 28 that are coupled to the selected memory cells 22 so that the storage circuit 32 is able to store corresponding data.
Whenever the control circuit 12 processes the write operation, cell current, which flows from the first bit line 26 or the second bit line 28 to the memory cell 22, occurs. For instance, in a case of nodes A and B of FIG. 2 being retained as low and high, respectively (i.e., logic xe2x80x9c0xe2x80x9d data is stored in the memory cell 22), when a logic xe2x80x9c1xe2x80x9d data write operation begins, the transistors T5 and T6 are driven conductive. However, since the transistor T1 still remains conductive during early burn-in write operation, the cell current flows from the first bit line 26 through the transistors T5 and T1 to a ground terminal 38 of the memory cell 22. Moreover, the potential of node B is still higher than the potential of the second bit line 28 during early burn-in write operation, thus another cell current flows from the transistor T6 to the second bit line 28. On the contrary, in the case of logic xe2x80x9c0xe2x80x9d data write operation, the transistor T2 still remains conductive and the potential of node A is still higher than the potential of the first bit line 26 during early burn-in write operation, thus two cell currents flow from the second bit line 28 through the transistors T6 and T2 to another ground terminal 39 of the memory cell 22 and flow from the transistor T5 to the first bit line 26, respectively. Since the current load-carrying ability of the bit lines 26 and 28 is limited (i.e., 700 mA per bit line) to avoid burning down the static random access memory, the apparatus 10 must select a limited number of memory cells 22 to test at a time. Therefore, the test time is relatively long.
It is therefore an object of the present invention to provide an apparatus and a method thereof for burn-in testing of a static random access memory (SRAM) that has fewer cell current occurrences.
The present invention, briefly summarized, discloses a method and an associated apparatus for burn-in testing of a static random access memory. The static random access memory comprises a plurality of word lines, a plurality of first bit lines, a plurality of second bit lines, and a plurality of memory cells for storing data. Each of the memory cells is coupled to a corresponding word line, a corresponding first bit line, and a corresponding second bit line. The apparatus comprises a power supply for applying a working voltage to the memory cells so as to drive the memory cells, and a control circuit electrically connected to the power supply for controlling operations of the apparatus. When the apparatus tests the static random access memory, the control circuit selects an appropriate number of memory cells to test and adjusts a potential of the word lines coupled to the selected memory cells to exceed a first voltage value. The control circuit also forms voltage gaps between the first bit lines and the second bit lines and adjusts the voltage gaps to exceed a second voltage value. When the potential of the word lines coupled to the selected memory cells exceeds the first voltage value and the voltage gaps exceed the second voltage value, the control circuit pulls up the working voltage from a third voltage value to a fourth voltage.
It is an advantage of the present invention that by adjusting the working voltage applied to the selected memory cells, the magnitude of currents flowing through bit lines is reduced effectively. Therefore, the apparatus according to the present invention is capable of testing more memory cells at a time. Moreover, the test time is shortened.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.